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CY62167EV18 mobl ? 16 mbit (1m x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05447 rev. *l revised june 29, 2011 16 mbit (1m x 16) static ram features very high speed: 55 ns wide voltage range: 1.65 v to 2.25 v ultra low standby power ? typical standby current: 1.5 ? a ? maximum standby current: 12 ? a ultra low active power ? typical active current: 2.2 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power down when deselected cmos for optimum speed and power offered in pb-free 48-ball very fine ball grid array (vfbga) packages functional description the CY62167EV18 is a high performance cmos static ram organized as 1m words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. place the device into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: the device is deselected (ce 1 high or ce 2 low); outputs are disabled (oe high); both byte high enable and byte low enable are disabled (bhe , ble high); and a write operation is in progress (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specif ied by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 10 for a complete description of read and write modes. power down circuit bhe ble ce 2 ce 1 1m 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 ce 2 ce 1 a 19 logic block diagram
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 2 of 16 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 5 data retention characteristics ....................................... 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definition .... ....................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 3 of 16 pin configuration product portfolio figure 1. 48-ball vfbga (6 8 1 mm) top view [ 1, 2] we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc notes 1. nc pins are not connected on the die. 2. ball h6 for the vfbga package can be used to upgrade to a 32 m density. 3. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 4. this part can be operated in the v cc range of 1.65 v?2.25 v at 55ns speed. it can also be operated in the v cc range of 2.2 v?3.6 v at 45ns speed. product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max CY62167EV18ll 1.65 1.8 2.25 55 2.2 4.0 25 30 1.5 12 cy62167ev30ll [4]
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 4 of 16 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied .......................................... ?55 c to + 125 c supply voltage to ground potential ....................... ?0.2 v to 2.45 v (v cc (max) + 0.2 v) dc voltage applied to outputs in high z state [5, 6] ....... ?0.2 v to 2.45 v (v cc (max) + 0.2 v) dc input voltage [5, 6] ..... ?0.2 v to 2.45 v (v cc (max) + 0.2 v) output current into outputs (low) ............................. 20 ma static discharge voltage........................................... >2001 v (mil-std-883, method 3015) latch up current....................................................... >200 ma operating range device range ambient temperature v cc [7] CY62167EV18ll industrial ?40 c to +85 c 1.65 v to 2.25 v electrical characteristics over the operating range parameter description test conditions 55 ns unit min typ [8] max v oh output high voltage i oh = ?0.1 ma 1.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.2 v v ih input high voltage v cc = 1.65 v to 2.25 v 1.4 ? v cc + 0.2 v v v il input low voltage v cc = 1.65 v to 2.25 v ?0.2 ? 0.4 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc (max) i out = 0 ma cmos levels ?25 30ma f = 1 mhz ? 2.2 4.0 ma i sb1 [9] automatic power down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2v, v in < 0.2 v) f = f max (address and data only), f = 0 (oe , and we ), v cc = v cc (max) ?1.5 12 ? a i sb2 [9] automatic power down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, or (bhe and ble ) > v cc ? 0.2 v, f = 0, v cc = v cc (max) ?1.5 12 ? a capacitance parameter [10] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 5. v il (min) = ?2.0 v for pulse durations less than 20 ns. 6. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 7. full device ac operation is based on a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 8. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 9. chip enables (ce 1 and ce 2 ), and byte enables (bhe and ble ) must be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating. 10. tested initially and after any design or proc ess changes that may affect these parameters.
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 5 of 16 thermal resistance parameter [11] description test conditions vfbga (6 8 1mm) unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 55 ? c/w ? jc thermal resistance (junction to case) 16 ? c/w figure 2. ac test loads and waveforms parameters 1.8 v unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.80 v data retention characteristics over the operating range parameter description conditions min typ [12] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [13] data retention current v cc = 1.0 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ??10 ? a t cdr [11] chip deselect to data retention time 0??ns t r [14] operation recovery time 55 ? ? ns figure 3. data retention waveform v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 notes 11. tested initially and after any design or proc ess changes that may affect these parameters. 12. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 13. chip enables (ce 1 and ce 2 ), and byte enables (bhe and ble ) must be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating. 14. full device operation requires linear v cc ramp from v dr to v cc (min) > 100 ? s or stable at v cc (min) > 100 ? s. 15. bhe . ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble . v cc (min) v cc (min) t cdr v dr > 1.0 v data retention mode t r ce 1 or v cc bhe . ble ce 2 or [15]
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 6 of 16 switching characteristics parameter [16, 17] description 55 ns unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [18] 5?ns t hzoe oe high to high z [18, 19] ?18ns t lzce ce 1 low and ce 2 high to low z [18] 10 ? ns t hzce ce 1 high and ce 2 low to high z [18, 19] ?18ns t pu ce 1 low and ce 2 high to power-up 0 ? ns t pd ce 1 high and ce 2 low to power-down ? 55 ns t dbe ble/bhe low to data valid ? 55 ns t lzbe ble /bhe low to low z [18] 10 ? ns t hzbe ble /bhe high to high z [18, 19] ?18ns write cycle [20] t wc write cycle time 55 ? ns t sce ce 1 low and ce 2 high to write end 40 ? ns t aw address setup to write end 40 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 40 ? ns t bw ble /bhe low to write end 40 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [18, 19] ?20ns t lzwe we high to low z [18] 10 ? ns notes 16. test conditions for all parameters other than tri-state parame ters are based on signal transition time of 1 v/ns, timing ref erence levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in ac test loads and waveforms on page 5 . 17. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 18. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 19. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the output enters a high impedance state. 20. the internal memory write time is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the ed ge of the signal that terminates the write.
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 7 of 16 switching waveforms figure 4. read cycle no. 1 (address transition controlled) . [21, 22] figure 5. read cycle no. 2 (oe controlled) [22, 23] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 21. the device is contin uously selected. oe , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . 22. we is high for read cycle. 23. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 8 of 16 figure 6. write cycle no. 1 (we controlled) [24, 25, 26] figure 7. write cycle no. 2 (ce 1 or ce 2 controlled) [24, 25, 26] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 27 ce 1 address ce 2 we data i/o oe bhe /ble notes 24. the internal memory write time is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. th e data input setup and hold timing must be referenced to the ed ge of the signal that terminates the write 25. data i/o is high impedance if oe = v ih . 26. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 27. during this period the i/os are in output state. do not apply input signals. t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 27 ce 1 address ce 2 we data i/o oe bhe /ble
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 9 of 16 figure 8. write cycle no. 3 (we controlled, oe low) [28] figure 9. write cycle no. 4 (bhe /ble controlled, oe low) [28] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 29 ce 1 address ce 2 we data i/o bhe /ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 29 ce 1 address ce 2 we data i/o bhe /ble notes 28. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 29. during this period the i/os are in output state. do not apply input signals.
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 10 of 16 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power hx [30] xxxxhigh z deselect/power-down standby (i sb ) x [30] lxxxxhigh z deselect/power-down standby (i sb ) x [30] x [30] x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) read active (i cc ) lhhllhhigh z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) lhhhhlhigh z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) write active (i cc ) lhlxlhhigh z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) note 30. the ?x? (don?t care) state for the chip enables in the truth table refer to the logic state (either high or low). intermedia te voltage levels on these pins is not permitted.
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 11 of 16 ordering code definition ordering information speed (ns) ordering code package diagram package type operating range 55 CY62167EV18ll-55bvi 51-85150 48-ball vfbga (6 8 1 mm) industrial CY62167EV18ll-55bvxi 48-ball vf bga (6 8 1 mm) (pb-free) cy62167ev30ll-45bvi [31] 51-85150 48-ball vfbga (6 8 1 mm) note 31. this part can be operated in the v cc range of 1.65 v to 2.25 v at 55 ns speed. it can also be operated in the v cc range of 2.2 v?3.6 v at 45ns speed. cy 621 = mobl sram family 621 6 7 density = 16 mbit company id: cy = cypress e bus width = x16 e = process technology 90 nm vxx v18 = voltage range (1.8 v typical) v30 = voltage range (3 v typical) ll low power 45/55 speed grade xxx package type: bvx: vfbga (pb-free) x temperature grade: i = industrial
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 12 of 16 package diagrams figure 10. 48-ball vfbga (6 8 1 mm), 51-85150 51-85150-*e 51-85150 *f
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 13 of 16 figure 11. 48-pin tsop i (12 mm x 18.4 mm x 1.0 mm), 51-85183 51-85153 *c
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 14 of 16 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine ball grid array we write enable symbol unit of measure c degrees celsius ? a microamperes ma milliamperes mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts
CY62167EV18 mobl ? document #: 38-05447 rev. *l page 15 of 16 document history page document title: CY62167EV18 mobl ? 16 mbit (1m x 16) static ram document number: 38-05447 rev. ecn no. orig. of change submission date description of change ** 202600 aju 01/23/2004 new data sheet *a 463674 nxr see ecn converted from ad vance information to preliminary changed v cc(max) from 2.20 v to 2.25 v removed ?l? bin and 35 ns speed bin from product offering changed ball e3 from dnu to nc removed redundant foot note on dnu changed the i sb2(typ) value from 1.3 ? a ? to ? 1.5 ? a changed the i cc(max) value from 40 ma to 25 ma changed the ac test load capacitance value from 50 pf to 30 pf corrected typo in data retention characteristics (t r ) from 100 s to t rc ns changed the i ccdr value from 8 ? a ? to ? 5 ? a changed t oha , t lzce , t lzbe , and t lzwe from 6 ns to 10 ns changed t lzoe from 3 ns to 5 ns changed t hzoe , t hzce , t hzbe , and t hzwe from 15 ns to 18 ns changed t sce , t aw , and t bw from 40 ns to 35 ns changed t pe from 30 ns to 35 ns changed t sd from 20 ns to 25 ns updated 48 ball fbga package information updated the ordering information table *b 469182 nsi see ecn minor change: moved to external web *c 619122 nxr see ecn replaced 45 ns speed bin with 55 ns speed bin *d 1130323 vkn see ecn converted from preliminary to final added footnote# 8 related i sb2 and i ccdr changed i sb1 and i sb2 spec from 10 ? a to 12 ? a changed i ccdr spec from 8 ? a to 10 ? a added footnote# 13 related ac timing parameters changed t wc spec from 45 ns to 55 ns changed t sce , t aw , t pwe , t bw spec from 35 ns to 40 ns changed t hzwe spec from 18 ns to 20 ns *e 1388287 vkn see ecn added 48-ball vfbga (6 x 7 x 1mm) package added footnote# 1 related to fbga package updated ordering information table *f 1664843 vkn/aesa see ecn added cy62167ev30ll-45bvi part in the ordering information table added footnote# 5 related to cy62167ev30ll-45bvi part *g 2675375 vkn/pyrs 03/17/2009 added CY62167EV18ll-55bvi part in the ordering information table *h 2904565 aju 04/05/2010 removed inactive part from the ordering information table.updated package diagrams. *i 2934396 vkn 06/03/10 added footnote #24 related to chip enable updated template *j 3006301 rame 08/12/2010 included bhe and ble in i sb1 , i sb2 , and i ccdr test conditions to reflect byte power down feature. removed 48-ball vfbga (6 x 7 x 1 mm) package related information. added acronyms and ordering code definition. format updates to match template. *k 3113908 pras 12/17/2010 updated figure 1 and package diagram. *l 3295175 rame 06/29/2011 updated package diagrams . added document conventions . removed reference to an10 64 sram system guidelines. added i sb1 to footnotes 9 and 13. modified ordering code definition . updated table of contents.
document #: 38-05447 rev. *l revised june 29, 2011 page 16 of 16 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all products and company names mentioned in this document may be the trademarks of their respective holders. CY62167EV18 mobl ? ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of of fices, solution centers, ma nufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.c om/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.co m/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cyp ress.com/go/usb wireless/rf cypress. com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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